【聯詠科技 Novatek 國際人才招募中 Global Talent Recruitment】Join a Top-Tier IC Design House!

 

Are you passionate about semiconductor and IC design? Novatek Microelectronics Corp. is looking for outstanding global engineering talent to join our team! Whether you're a Master's graduate ready to shine or a 1st-year Master's student seeking a summer internship, your stage is here!

你對半導體與 IC 設計充滿熱情嗎？頂尖 IC 設計大廠「聯詠科技」正在尋找全球優秀的工程人才！無論你是準備大展身手的碩博士畢業生，還是尋找暑期實習的碩一菁英，這裡都有屬於你的舞台！

【We Want YOU | 招募條件】

Education / 學歷條件: Master’s degree or above for full-time roles; 1st-year Master’s students or above preferred for Summer Internships. (正職職缺需碩士以上；暑期實習優先考慮碩一以上)

Majors / 科系要求: Electrical Engineering (EE), Electronic Engineering, or related fields. (電機 / 電子工程相關系所)

Language / 語言條件: Basic Mandarin communication skills + Excellent English proficiency (Listening, Speaking, Reading, Writing) for daily work and technical discussions. (具備基礎中文溝通能力，且具備良好英文聽說讀寫能力，能順暢進行技術討論)

【Job Openings & Requirements | 招募職缺與技術需求】

Analog IC Design Engineer (類比 IC 設計工程師)

Familiar with HSPICE, MATLAB, Laker, Spectre, SIMPLIS, and Cadence Virtuoso.

Strong understanding of analog circuit design and semiconductor device fundamentals.

Experience with UNIX and Tcl/Tk-based GUI tools is a plus.

Experience in analog and mixed-signal circuit design is preferred.

Digital IC Design Engineer (數位 IC 設計工程師)

Knowledge of VLSI, digital IC design, and IC design flow is required.

Proficiency in Verilog or SystemVerilog is required.

Familiarity with C/C++, Python, UVM, and SpyGlass is preferred.

Knowledge of Python, Perl, or Tcl is a plus.

Physical Design Engineer (實體設計工程師)

Completion of VLSI-related coursework with a solid foundation in digital logic design.

Hands-on experience in VLSI laboratory projects or TSRI (formerly CIC) training programs (e.g., Cell-Based IC Physical Design using Innovus or IC Compiler) is highly desirable.

Research experience in EDA tools or methodologies is a plus.

Design Verification Engineer (設計驗證工程師)

Hands-on experience in whole-chip testbench development (IP-level and SoC-level).

Experience in high-speed I/O protocol verification (PCIe, USB 3.x, USB4, DDR4, LPDDR4).

Experience using commercial Verification IP (VIP), such as Synopsys or Cadence VIP.

Familiarity with verification methodologies (UVM, VMM, or OVM).

Proficiency in Verilog/SystemVerilog and scripting languages (Python, Perl, or Tcl).

【How to Apply | 應徵方式】

Ready to take on the challenge and innovate with Novatek?

Please scan the QR Code in the image below to submit your English resume!

準備好迎接挑戰了嗎？

請掃描下方圖片中的 QR Code，立刻投遞您的英文履歷！